System and method for improving cache performance

ABSTRACT

A method, computer program product, and computing system for maintaining a queue of cache operations to be performed within a cache memory system. The cache operations include one or more of cache write operations and cache read operations. The cache operations within the queue are reordered based, at least in part, upon a maximum acceptable write operation latency.

RELATED APPLICATIONS

The subject application is a continuation application of U.S. patent application with Ser. No. 12/895,021, filed on Sep. 30, 2010, the entire content of which is herein incorporated by reference.

TECHNICAL FIELD

This disclosure relates to cache memory systems and, more particularly, to systems and methods for improving the performance of cache memory systems.

BACKGROUND

Storing and safeguarding electronic data is of paramount importance in modern business. Accordingly, various systems may be employed to protect such electronic data.

The use of solid-state storage devices is increasing in popularity. A solid state storage device is a data storage device that uses solid-state memory to store persistent data. A solid-state storage device may emulate (and therefore replace) a conventional hard disk drive. Additionally/alternatively, a solid state storage device may be used within a cache memory system. With no moving parts, a solid-state storage device largely eliminates (or greatly reduces) seek time, latency and other electromechanical delays and failures associated with a conventional hard disk drive.

SUMMARY OF DISCLOSURE

In a first implementation, a computer implemented method includes maintaining a queue of cache operations to be performed within a cache memory system. The cache operations include one or more of cache write operations and cache read operations. The cache operations within the queue are reordered based, at least in part, upon a maximum acceptable write operation latency.

One or more of the following features may be included. The cache memory system may be a non-volatile, solid-state, cache memory system. The maximum acceptable write operation latency may be defined. The maximum acceptable write operation latency may be a defined period of time. The maximum acceptable write operation latency may be a defined number of cache write operations.

Reordering the cache operations within the queue based, at least in part, upon a maximum acceptable write operation latency may include: repositioning a cache read operation within the queue so that it is serviced before a cache write operation within the queue. Reordering the cache operations within the queue based, at least in part, upon a maximum acceptable write operation latency my include: repositioning a cache read operation within the queue so that it is the next operation serviced within the queue.

In another implementation, a computer program product resides on a computer readable medium that has a plurality of instructions stored on it. When executed by a processor, the instructions cause the processor to perform operations including maintaining a queue of cache operations to be performed within a cache memory system. The cache operations include one or more of cache write operations and cache read operations. The cache operations within the queue are reordered based, at least in part, upon a maximum acceptable write operation latency.

One or more of the following features may be included. The cache memory system may be a non-volatile, solid-state, cache memory system. The maximum acceptable write operation latency may be defined. The maximum acceptable write operation latency may be a defined period of time. The maximum acceptable write operation latency may be a defined number of cache write operations.

Reordering the cache operations within the queue based, at least in part, upon a maximum acceptable write operation latency may include: repositioning a cache read operation within the queue so that it is serviced before a cache write operation within the queue. Reordering the cache operations within the queue based, at least in part, upon a maximum acceptable write operation latency my include: repositioning a cache read operation within the queue so that it is the next operation serviced within the queue.

In another implementation, a computing system includes at least one processor and at least one memory architecture coupled with the at least one processor. A first software module is executed on the at least one processor and the at least one memory architecture. The first software module is configured to perform operations including maintaining a queue of cache operations to be performed within a cache memory system. The cache operations include one or more of cache write operations and cache read operations. A second software module is executed on the at least one processor and the at least one memory architecture. The second software module is configured to perform operations including reordering the cache operations within the queue based, at least in part, upon a maximum acceptable write operation latency.

One or more of the following features may be included. The cache memory system may be a non-volatile, solid-state, cache memory system. The maximum acceptable write operation latency may be defined. The maximum acceptable write operation latency may be a defined period of time. The maximum acceptable write operation latency may be a defined number of cache write operations.

Reordering the cache operations within the queue based, at least in part, upon a maximum acceptable write operation latency may include: repositioning a cache read operation within the queue so that it is serviced before a cache write operation within the queue. Reordering the cache operations within the queue based, at least in part, upon a maximum acceptable write operation latency may include: repositioning a cache read operation within the queue so that it is the next operation serviced within the queue.

The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features and advantages will become apparent from the description, the drawings, and the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagrammatic view of a storage system and a data caching process coupled to a distributed computing network;

FIG. 2 is a diagrammatic view of the storage system of FIG. 1;

FIG. 3 is a flowchart of the data caching process of FIG. 1; and

FIG. 4 is a diagrammatic view of a queue maintained by the data caching process of FIG. 1.

Like reference symbols in the various drawings indicate like elements.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

As will be appreciated by one skilled in the art, the present disclosure may be embodied as a method, system, or computer program product. Accordingly, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.” Furthermore, the present disclosure may take the form of a computer program product on a computer-usable storage medium having computer-usable program code embodied in the medium.

Any suitable computer usable or computer readable medium may be utilized. The computer-usable or computer-readable medium may be, for example but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, device, or propagation medium. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a transmission media such as those supporting the Internet or an intranet, or a magnetic storage device. Note that the computer-usable or computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted, or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory. In the context of this document, a computer-usable or computer-readable medium may be any medium that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The computer-usable medium may include a propagated data signal with the computer-usable program code embodied therewith, either in baseband or as part of a carrier wave. The computer usable program code may be transmitted using any appropriate medium, including but not limited to the Internet, wireline, optical fiber cable, RF, etc.

Computer program code for carrying out operations of the present disclosure may be written in an object oriented programming language such as Java, Smalltalk, C++ or the like. However, the computer program code for carrying out operations of the present disclosure may also be written in conventional procedural programming languages, such as the “C” programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).

The present disclosure is described below with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function/act specified in the flowchart and/or block diagram block or blocks.

The computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

System Overview:

Referring to FIG. 1, there is shown data caching process 10 that may reside on and may be executed by storage system 12, which may be connected to network 14 (e.g., the Internet or a local area network). Examples of storage system 12 may include, but are not limited to: a Network Attached Storage (NAS) system, a Storage Area Network (SAN), a personal computer with a memory system, a server computer with a memory system, and a cloud-based device with a memory system.

As is known in the art, a SAN may include one or more of a personal computer, a server computer, a series of server computers, a mini computer, a mainframe computer, a RAID device and a NAS system. The various components of storage system 12 may execute one or more operating systems, examples of which may include but are not limited to: Microsoft Windows XP Server™ Novell Netware™; Redhat Linux™, Unix, or a custom operating system, for example.

As will be discussed below in greater detail, data caching process 10 may maintain a queue of cache operations to be performed within a cache memory system. The cache operations may include one or more of cache write operations and cache read operations. Data caching process 10 may reorder the cache operations within the queue based, at least in part, upon a maximum acceptable write operation latency.

The instruction sets and subroutines of data caching process 10, which may be stored on storage device 16 included within storage system 12, may be executed by one or more processors (not shown) and one or more memory architectures (not shown) included within storage system 12. Storage device 16 may include but is not limited to: a hard disk drive; a tape drive; an optical drive; a RAID device; a random access memory (RAM); and a read-only memory (ROM).

Network 14 may be connected to one or more secondary networks (e.g., network 18), examples of which may include but are not limited to: a local area network; a wide area network; or an intranet, for example.

Various data requests (e.g. data request 20) may be sent from client applications 22, 24, 26, 28 to storage system 12. Examples of data request 20 may include but are not limited to data write requests (i.e. a request that data be written to storage system 12) and data read requests (i.e. a request that data be read from storage system 12).

The instruction sets and subroutines of client applications 22, 24, 26, 28, which may be stored on storage devices 30, 32, 34, 36 (respectively) coupled to client electronic devices 38, 40, 42, 44 (respectively), may be executed by one or more processors (not shown) and one or more memory architectures (not shown) incorporated into client electronic devices 38, 40, 42, 44 (respectively). Storage devices 30, 32, 34, 36 may include but are not limited to: hard disk drives; tape drives; optical drives; RAID devices; random access memories (RAM); read-only memories (ROM), and all forms of flash memory storage devices. Examples of client electronic devices 38, 40, 42, 44 may include, but are not limited to, personal computer 38, laptop computer 40, personal digital assistant 42, notebook computer 44, a server (not shown), a data-enabled, cellular telephone (not shown), and a dedicated network device (not shown).

As discussed above, examples of storage system 12 may include, but are not limited to: a Network Attached Storage (NAS) system, a Storage Area Network (SAN), a personal computer with a memory system, a server computer with a memory system, and a cloud-based device with a memory system. Accordingly, storage system 12 (as described above, as described below, or in a simpler form (e.g., a single hard drive without redundancy) may be included within any of a variety of devices. For example, storage system 12 may be e.g., a memory system within a desktop computer having a single hard drive, a RAID controller card within a server computer that controls multiple hard drives, a memory system within a stand-alone network attached storage device, a memory system within a laptop computer, a memory system within a smart phone, or a cache system included within a hard disk drive.

Users 46, 48, 50, 52 may access storage system 12 directly through network 14 or through secondary network 18. Further, storage system 12 may be connected to network 14 through secondary network 18, as illustrated with link line 54.

The various client electronic devices may be directly or indirectly coupled to network 14 (or network 18). For example, personal computer 38 is shown directly coupled to network 14 via a hardwired network connection. Further, notebook computer 44 is shown directly coupled to network 18 via a hardwired network connection. Laptop computer 40 is shown wirelessly coupled to network 14 via wireless communication channel 56 established between laptop computer 40 and wireless access point (i.e., WAP) 58, which is shown directly coupled to network 14. WAP 58 may be, for example, an IEEE 802.11a, 802.11b, 802.11g, Wi-Fi, and/or Bluetooth device that is capable of establishing wireless communication channel 56 between laptop computer 40 and WAP 58. Personal digital assistant 42 is shown wirelessly coupled to network 14 via wireless communication channel 60 established between personal digital assistant 42 and cellular network/bridge 62, which is shown directly coupled to network 14.

As is known in the art, all of the IEEE 802.11x specifications may use Ethernet protocol and carrier sense multiple access with collision avoidance (i.e., CSMA/CA) for path sharing. The various 802.11x specifications may use phase-shift keying (i.e., PSK) modulation or complementary code keying (i.e., CCK) modulation, for example. As is known in the art, Bluetooth is a telecommunications industry specification that allows e.g., mobile phones, computers, and personal digital assistants to be interconnected using a short-range wireless connection.

Client electronic devices 38, 40, 42, 44 may each execute an operating system, examples of which may include but are not limited to Microsoft Windows™, Microsoft Windows CE™, Redhat Linux™, or a custom operating system.

The Data Caching Process:

For the following discussion, client application 22 is going to be described for illustrative purposes. However, this is not intended to be a limitation of this disclosure, as other client applications (e.g., client applications 24, 26, 28) may be equally utilized.

For illustrative purposes, storage system 12 will be described as being a network-based storage system that includes a plurality of electro-mechanical backend storage devices. However, this is for illustrative purposes only and is not intended to be a limitation of this disclosure, as other configurations are possible and are considered to be within the scope of this disclosure. For example and as discussed above, storage system 12 may be a personal computer that includes a single electro-mechanical storage device.

Referring also to FIG. 2, storage system 12 may include a storage initiator device (e.g. storage initiator device 100), and a plurality of storage targets T_(1-n) (e.g. storage targets 102, 104, 106, 108). Storage targets 102, 104, 106, 108 may be configured to provide various levels of performance and/or high availability. For example, one or more of storage targets 102, 104, 106, 108 may be configured as a RAID 0 array, in which data is striped across storage targets. By striping data across a plurality of storage targets, improved performance may be realized. However, RAID 0 arrays do not provide a level of high availability. Additionally/alternatively, one or more of storage targets 102, 104, 106, 108 may be configured as a RAID 1 array, in which data is mirrored between storage targets. By mirroring data between storage targets, a level of high availability is achieved as multiple copies of the data are stored within storage system 12.

While storage targets 102, 104, 106, 108 are discussed above as being configured in a RAID 0 or RAID 1 array, this is for illustrative purposes only and is not intended to be a limitation of this disclosure, as other configurations are possible. For example, storage targets 102, 104, 106, 108 may be configured as a RAID 3, RAID 4, RAID 5 or RAID 6 array.

While in this particular example, storage system 12 is shown to include four storage targets (e.g. storage targets 102, 104, 106, 108), this is for illustrative purposes only and is not intended to be a limitation of this disclosure. Specifically, the actual number of storage targets may be increased or decreased depending upon e.g. the level of redundancy/performance/capacity required.

Storage system 12 may also include one or more coded targets 110. As is known in the art, a coded target may be used to store coded data that may allow for the regeneration of data lost/corrupted on one or more of storage targets 102, 104, 106, 108. An example of such a coded target may include but is not limited to a hard disk drive that is used to store parity data within a RAID array.

While in this particular example, storage system 12 is shown to include one coded target (e.g., coded target 110), this is for illustrative purposes only and is not intended to be a limitation of this disclosure. Specifically, the actual number of coded targets may be increased or decreased depending upon e.g. the level of redundancy/performance/capacity required.

A combination of storage targets 102, 104, 106, 108 and coded target 110 may form non-volatile, electro-mechanical memory system 112.

The manner in which storage system 12 is implemented may vary depending upon e.g. the level of redundancy/performance/capacity required. For example, storage system 12 may be a RAID device in which storage initiator device 100 is a RAID controller card and storage targets 102, 104, 106, 108 and/or coded target 110 are individual “hot-swappable” hard disk drives. An example of such a RAID device may include but is not limited to an NAS device. Alternatively, storage system 12 may be configured as a SAN, in which storage initiator device 100 may be e.g., a server computer and each of storage targets 102, 104, 106, 108 and/or coded target 110 may be a RAID device and/or computer-based hard disk drive. Further still, one or more of storage targets 102, 104, 106, 108 and/or coded target 110 may be a SAN.

In the event that storage system 12 is configured as a SAN, the various components of storage system 12 (e.g. storage initiator device 100, storage targets 102, 104, 106, 108, and coded target 110) may be coupled using network infrastructure 114, examples of which may include but are not limited to an Ethernet (e.g., Layer 2 or Layer 3) network, a fiber channel network, an InfiniBand network, or any other circuit switched/packet switched network.

Storage initiator device 100 may execute all or a portion of data caching process 10. The instruction sets and subroutines of data caching process 10, which may be stored on a storage device (e.g., storage device 16) coupled to storage initiator device 100, may be executed by one or more processors (not shown) and one or more memory architectures (not shown) included within storage initiator device 100. Storage device 16 may include but is not limited to: a hard disk drive; a tape drive; an optical drive; a RAID device; a random access memory (RAM); and a read-only memory (ROM).

As discussed above, various data requests (e.g. data request 20) may be sent from client applications 22, 24, 26, 28 to storage system 12, and examples of data request 20 may include but are not limited to data write request 116 (i.e. a request that data extent 118 be written to storage system 12) and data read request 120 (i.e. a request that data extent 118 be read from storage system 12).

As will be discussed below in greater detail, storage initiator device 100 may include input-output logic 122 (e.g., a network interface card), processing logic 124, volatile, solid-state, cache memory system 126 (e.g., a dynamic RAM cache memory system), and non-volatile, solid-state, cache memory system 128 (e.g., a flash-based, cache memory system).

During operation of storage initiator device 100, data (e.g. data extent 118) to be written to storage system 12 may be received by input-output logic 122 (e.g. from network 14 and/or network 18) and processed by processing logic 124. As will be discussed below in greater detail, processing logic 124 may initially store data extent 118 within volatile, solid-state, cache memory system 126, and may subsequently destage data extent 118 to non-volatile, solid-state, cache memory system 128 by gathering a plurality of data extents (e.g., data extent 118) within volatile, solid-state, cache memory system 126, apportioning the data extents into a plurality of data elements (e.g., data elements 130, 132, 134, 136), and destaging this plurality of data elements (e.g., data elements 130, 132, 134, 136) as a single data segment (e.g., data segment 138) to non-volatile, solid-state, cache memory system 128. Processing logic 124 may then destage data segment 138 to the storage targets (e.g. storage targets 102, 104, 106, 108) included within non-volatile, electromechanical memory system 112. Additionally, processing logic 124 may calculate and store coded data on coded target 110 (included within non-volatile, electromechanical memory system 112) that may allow for the regeneration of data lost/corrupted on one or more of storage targets 102, 104, 106, 108.

While not as fast as volatile, solid-state, cache memory system 126, non-volatile, solid-state, cache memory system 128 may be considerably quicker than non-volatile, electromechanical memory system 112. Accordingly, non-volatile, solid-state, cache memory system 128 may be sized so that the number of times that non-volatile, electromechanical memory system 112 is accessed may be reduced. Accordingly, by sizing non-volatile, solid-state, cache memory system 128 so that non-volatile, solid-state, cache memory system 128 retains a quantity of data sufficient to satisfy a significant quantity of data requests (e.g., data request 20), the overall performance of storage system 12 may be enhanced.

Referring also to FIGS. 3-4 and as discussed above, data caching process 10 may maintain 100 a queue (e.g., 300) of cache operations (e.g., write operations 1-5 and read operations 1-3) to be performed within a cache memory system (e.g., non-volatile, solid-state, cache memory system 128). Data caching process 10 may reorder 202 the cache operations (e.g., write operations 1-5 and read operations 1-3) within queue 300 based, at least in part, upon a maximum acceptable write operation latency.

As discussed above, various data requests (e.g. data request 20) may be sent from client applications 22, 24, 26, 28 to storage system 12, and examples of data request 20 may include but are not limited to data write request 116 (i.e. a request that data extent 118 be written to storage system 12) and data read request 120 (i.e. a request that data extent 118 be read from storage system 12).

As these data requests arrive, data caching process 10 places them within queue 300 for subsequent execution as read and write operations with respect to non-volatile, solid-state, cache memory system 128. Unfortunately and as is known in the art, it takes considerably longer for a write operation to be executed by a non-volatile solid-state device than it does for a read operation. Specifically, it may take ten to one hundred times as long for a write operation to be executed (with respect to a read operation). Accordingly it is foreseeable that in the event that a read operation is queued behind a plurality of write operations, the time delay (or latency) before the read operation is executed by a non-volatile solid-state device may be unacceptably long. Further, when a read operation is awaiting execution, a user (e.g., user 46, user 48, user 50, user 52) is waiting for the requested data. This is typically in contrast with a write operation, wherein data provided by a user (e.g., user 46, user 48, user 50, user 52) is merely waiting to be written to a cache memory system (e.g., non-volatile, solid-state, cache memory system 128). Accordingly, data caching process 10 may reorder 202 the cache operations (e.g., write operations 1-5 and read operations 1-3) within queue 300 based, at least in part, upon a maximum acceptable write operation latency.

Data caching process 10 may define 204 (e.g., algorithmically) a maximum acceptable write operation latency. Data caching process 10 may allow the maximum acceptable write operation latency to be defined as a period of time or as a defined number of cache write operations. For example, assume that it takes one millisecond to execute a write operation within non-volatile, solid-state, cache memory system 128. According, data caching process 10 may allow an administrator to define the maximum acceptable write operation latency as three milliseconds (e.g., a read operation will wait a maximum of three milliseconds before execution). Alternatively, data caching process 10 may allow an administrator to define the maximum acceptable write operation latency as three write operations (e.g., a read operation will wait a maximum of three write operations before execution).

In this particular example, queue 300 is shown to include a plurality of slots (e.g., slots 302, 304, 306, 308, 310, 312, 314, 316) into which the various read and write operations are sequentially placed. Assume for illustrative purposes that slot 302 is the highest order slot (e.g., the first to be executed) and slot 316 is the lowest order slot (e.g., the last to be executed). Further, assume that once an operation (e.g., write operation #1) is executed, the operation (e.g., write operation #2) in the lower-order adjacent slot (e.g., slot 304) is promoted to the higher-order adjacent slot (e.g., slot 302). Accordingly, queue 300 may function in a similar manner to that of a FIFO buffer.

While in this particular example, queue 300 is shown to include eight slots (e.g., slots 302, 304, 306, 308, 310, 312, 314, 316), this is for illustrative purpose only and is not intended to be a limitation of this disclosure, as other configurations are possible and are considered to be within the scope of this disclosure. For example, the number of slots within queue 300 may be increased or decreased based upon the anticipated needs of data caching process 10 and non-volatile, solid-state, cache memory system 128.

Assume for illustrative purposes that four write operations (e.g., write operation #1, write operation #2, write operation #3, write operation #4) are received by data caching process 10 and place into slots 302, 304, 306, 308 respectively. Further assume that two read operation (e.g., read operation #1, read operation #2) are received by data caching process 10, followed by a write operation (e.g., write operation #5), and then a read operation (e.g., read operation #3), which are placed into slots 310, 312, 314, 316 respectively.

Continuing with the above-stated example in which the administrator defined 204 a maximum acceptable write operation latency of three write operations (e.g., a read operation will wait a maximum of three write operations before execution), data caching process 10 may maintain 100 queue 300 of cache operations (e.g., write operations 1-5 and read operations 1-3) to be performed within non-volatile, solid-state, cache memory system 128. However, if data caching process 10 places read operation #1 into slot 310 of queue 300, the maximum acceptable write operation latency of three write operations will be violated, as four write operations (e.g., write operation #1 through write operation #4) which are resident within slots 302, 304, 306, 308 respectively would need to be executed prior to executing read operation #1 (which was to be placed into slot 310). Accordingly, data caching process 10 may reorder 202 the cache operations within queue 300 based, at least in part, upon the maximum acceptable write operation latency of three write operations.

When reordering 202 the cache operations within queue 300, data caching process may e.g., reposition a cache read operation within the queue so that it is serviced before a cache write operation within the queue; or reposition a cache read operation within the queue so that it is the next operation serviced within the queue.

Accordingly, data caching process 10 may move read operation #1 from slot 310 to slot 302 (as illustrated by arrow 320), resulting in each of write operation #1, write operation #2, write operation #3 and write operation #4 being shifted backward one slot. Alternatively, data caching process 10 may move read operation #1 from slot 310 to slot 308 (as illustrated by arrow 322), resulting in write operation #4 each being shifted backward one slot. Either one of these moves concerning read operation #1 results in read operation #1 meeting the requirements of a maximum acceptable write operation latency of three write operations.

Data caching process 10 may need to effectuate further reordering 202 of the cache operations within queue 300 to address the maximum acceptable write operation latency with respect to read operation #2 (which is in slot 312 and is currently positioned behind four write operations) and read operation #3 (which is in slot 316 and currently positioned behind five write operations).

While data caching process 10 is described above as being utilized with respect to all cache write operations, this is for illustrative purposes only and is not intended to be a limitation of this disclosure, as other configurations are possible and are considered to be within the scope of this disclosure. For example, data caching process 10 may only be utilized on a subset of cache write operations. Accordingly, data caching process 10 may only move cache read operations in front of those cache write operations that are the result of cache misses. For example, whenever a read request (e.g., read request 120) is received concerning non-volatile, solid-state, cache memory system 128, data caching process 10 may examine non-volatile, solid-state, cache memory system 128 to determine if the requested data is present within non-volatile, solid-state, cache memory system 128. If data caching process 10 determines that the requested data is not present (i.e., a cache miss) within non-volatile, solid-state, cache memory system 128, data caching process 10 may read the requested data from non-volatile, electro-mechanical memory system 112 and write the requested data that was retrieved from non-volatile, electro-mechanical memory system 112 to non-volatile, solid-state, cache memory system 128. Accordingly, data caching process 10 may be configured to only move cache read operations in front of those cache write operations that are the result of such cache misses.

As will be appreciated by one skilled in the art, the present disclosure may be embodied as a method, system, or computer program product. Accordingly, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.” Furthermore, the present disclosure may take the form of a computer program product on a computer-usable storage medium having computer-usable program code embodied in the medium.

The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosure in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The embodiment was chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others of ordinary skill in the art to understand the disclosure for various embodiments with various modifications as are suited to the particular use contemplated.

A number of implementations have been described. Having thus described the disclosure of the present application in detail and by reference to embodiments thereof, it will be apparent that modifications and variations are possible without departing from the scope of the disclosure defined in the appended claims. 

What is claimed is:
 1. A computer implemented method comprising: maintaining a queue of cache operations to be performed within a cache memory system, wherein the cache operations include one or more of a cache write operation and a cache read operation; and reordering the cache operations within the queue based, at least in part, upon a maximum acceptable write operation latency, wherein the maximum acceptable write operation latency is a defined period of time.
 2. The computer implemented method of claim 1 wherein the cache memory system is a non-volatile, solid-state, cache memory system.
 3. The computer implemented method of claim 1 further comprising: defining the maximum acceptable write operation latency.
 4. The computer implemented method of claim 1 wherein reordering the cache operations within the queue based, at least in part, upon the maximum acceptable write operation latency includes: repositioning the cache read operation within the queue so that it is serviced before the cache write operation within the queue.
 5. A computer program product residing on a non-transitory computer readable medium having a plurality of instructions stored thereon which, when executed by a processor, cause the processor to perform operations comprising: maintaining a queue of cache operations to be performed within a cache memory system, wherein the cache operations include one or more of a cache write operation and a cache read operation; and reordering the cache operations within the queue based, at least in part, upon a maximum acceptable write operation latency, wherein the maximum acceptable write operation latency is a defined period of time.
 6. The computer program product of claim 5 wherein the cache memory system is a non-volatile, solid-state, cache memory system.
 7. The computer program product of claim 5 further comprising: defining the maximum acceptable write operation latency.
 8. The computer program product of claim 5 wherein reordering the cache operations within the queue based, at least in part, upon the maximum acceptable write operation latency includes: repositioning the cache read operation within the queue so that it is serviced before the cache write operation within the queue.
 9. A computing system comprising: at least one processor; at least one memory architecture coupled with the at least one processor; a first module executed on the at least one processor and the at least one memory architecture, wherein the first software module is configured to perform operations including maintaining a queue of cache operations to be performed within a cache memory system, wherein the cache operations include one or more of a cache write operation and a cache read operation; and a second module executed on the at least one processor and the at least one memory architecture, wherein the second software module is configured to perform operations including reordering the cache operations within the queue based, at least in part, upon a maximum acceptable write operation latency, wherein the maximum acceptable write operation latency is a defined period of time.
 10. The computing system of claim 9 wherein the cache memory system is a non-volatile, solid-state, cache memory system.
 11. The computing system of claim 9 further comprising: a third module executed on the at least one processor and the at least one memory architecture, wherein the third software module is configured to perform operations including defining the maximum acceptable write operation latency.
 12. The computing system of claim 9 wherein reordering the cache operations within the queue based, at least in part, upon the maximum acceptable write operation latency includes: repositioning the cache read operation within the queue so that it is serviced before the cache write operation within the queue. 